The field of invention is data conversion, more precisely, this invention relates to oversampled mismatch-shaping digital-to-analog converters.
In electronic circuits, signal processing is most efficiently implemented when the signals are represented digitally. Real-world signals are analog, and the conversion between analog and digital signals is, therefore, an important application. The following discussion centers around the implementation of digital-to-analog (D/A) converters, which may be used either directly for the D/A conversion of digital signals, or as an important element for the implementation of analog-to-digital (A/D) converters.
3.1 Binary-Weighted D/A Converters
A thorough discussion of the ideal operation of and several techniques for the implementation of D/A converters can be found in a Ph.D. thesis by Jesper Steensgaard [High-Performance Data Converters, Ph.D. thesis by Jesper Steensgaard, Jan. 20, 1999, The Technical University of Denmark, Lyngby Denmark]. D/A converters are often implemented by separating the digital input signal d(k) into a sum of digital subsignals d(k)=d1(k)+d2(k)+. . . +dN(k) which are D/A converted individually, thereby generating the analog subsignals a1(k),a2(k), . . . , aN(k). The overall analog output signal a(k) is the sum of the analog subsignals, a(k)=a1(k)+a2(k)+. . . +aN(k). In the ideal case, the analog subsignals are proportional to the corresponding digital subsignals, i.e. ai(k)=Kdi(k), ixcex5{1, 2, . . . , N}, where K is the same dimensional constant (for example 1 milli Volt or 1 micro Ampere) for all the subsignals. In that case the operation is considered to be ideal a(k)=Kd(k). Offsets are often acceptable.
For ease of implementation, the digital subsignals will typically be of low resolution, i.e., the digital subsignals di(k) are sequences of values selected from sets Si consisting of each only a few elements. For example, binary-weighted D/A converters are very simple D/A converters that separate the digital input signal d(k) bitwise into digital subsignals di(k), which each attain only two values, Si={0, ki}, the difference of which, ki, is proportional to a power of two, 2i. Binary-weighted D/A converters operate by letting each two-level digital subsignal turn on or off an analog source which is scaled according to ki, whereby the analog subsignals ai(k) are generated. To simplify the summation of the analog subsignals, the analog sources will typically be charge or current sources. FIG. 1 shows a typical 4-bit binary-weighted current-steering D/A converter with gain K=1 mA.
3.2 Errors Caused by Mismatch of the Analog Sources
Electrical parameters are unfortunately not well controlled in the processing of integrated electrical circuits. Thus, the gains Ki of the sub D/A converters will generally not all attain their nominal value K, nor will they match perfectly their nominal ratios. This implies that a typical binary-weighted D/A converter is not fully described by the gain factor K because, for any gain value {circumflex over (K)}, the error e(k)=a(k)xe2x88x92d(k){circumflex over (K)} will be a nonconstant function of the digital input signal d(k). In other words, the D/A converter is characterized by a nonlinear behavior, which is undesirable.
FIG. 2 shows an example of an unit-element D/A converter. Unit-element D/A converters have the property that the digital input signal d(k) is separated into digital subsignals di(k) which all attain only values from the same set S consisting of only two elements, say 0 and 1. Hence, the analog sources used to implement the sub D/A converters all have the same nominal value; they are called unit elements. Unit-element D/A converters based on deterministic and time-invariant digital encoders [32] are characterized by a good local linearity (the so-called differential nonlinearity), but the overall/absolute linearity (the so-called integral nonlinearity) is equivalent to that of binary-weighted D/A converters.
3.3 Mismatch-Matching D/A Converters
As opposed to binary-weighted D/A converters, the digital subsignals di(k) used in unit-element D/A converters are not necessarily uniquely defined functions of the digital input signal d(k). Consider the 5-level unit-element D/A converter shown in FIG. 2. If, for example, the digital input signal d(k) has the value 1, then the digital encoder [32] can assign the value 1 to any one of the 4 digital subsignals di(k), and thus, assign the value 0 to the other 3 digital subsignals. In other words, for d(k)=1, the correct nominal operation can be achieved in 4 different ways. Similarly, when the digital input signal d(k) has either the value 2 or 3, the nominal operation can be achieved in respectively 6 and 4 different ways. The digital subsignals di(k) are uniquely defined when the value of the digital input signal d(k) is either 0 or 4.
D/A converters, for which the nominally correct analog output signal can be generated in multiple ways, and for which harmonic distortion due to mismatch of electrical parameters is avoided by alternating between the multiple options, are said to be mismatch-shaping.
3.3.1 Randomized-Scrambling Encoders
L. Richard Carley explained [xe2x80x9cA Noise-Shaping Coder Topology for 15+ Bit Convertersxe2x80x9d, L. Richard Carley, IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, April 1989] that if the digital encoder [32] for every new input sample selects randomly one of the valid combinations, then the unit-element D/A converter will be perfectly linear. Carley proposed an implementation, shown in FIG. 3, where a thermometer-type digital encoder [36] is followed by a butterfly-type randomizing scrambler [38]. The thermometer-type digital encoder [36] generates the digital intermediate signals, b1(k), b2(k), b3(k), and b4(k), according to the deterministic, memoryless, and time-invariant operation expressed by the truth table shown in FIG. 4. The randomizing scrambler [38] generates the digital subsignals di(k) by randomly (or, more generally, pseudo-randomly) interchanging the intermediate signals bi(k). In other words, the subsignals are randomly generated permutations of the intermediate signals. Carley explained that a unit-element DAC based on this type of randomized-scrambling digital encoder [34] will be perfectly linear and have a gain which is exactly the average value of the employed sub D/A converters"" gains.
Instead of harmonic distortion, the overall analog output signal a(k) will include a stochastic signal component e(k) (noise) having uniform spectral power density (similar to white noise). The Nyquist-band power of e(k) is proportional to the mismatch of the employed analog sources. For example, if the relative mismatch of the analog sources is in the order of 0.1%, which is a typical value, then the analog output signal a(k) will have a signal-to-noise ratio (SNR) of approximately 60 dB when evaluated in the Nyquist frequency range. Usually D/A converters are operated somewhat oversampled, i.e., the sampling frequency fs is usually more than twice the considered signal bandwidth fb, in which case the inband SNR will be somewhat better than 60 dB. However, the inband SNR performance is improved only 10 dB for each ten-fold increase of the oversampling ratio (OSR=fs/(2fb)). Thus, 100 dB performance requires in the order of 10,000 times oversampling, which usually is not feasible.
Randomized-scrambling unit-element encoders are said to be zero-order mismatch-shaping because the error signal is not suppressed in the signal band.
3.3.2 Element-Rotation-Scheme (ERS) Encoders
U.S. Pat. No. 5,138,317 to Michael J. Story describes that by generating the digital subsignals as a certain function of the present and previous samples of the digital input signal d(k), the unit-element D/A converter will be perfectly linear and have a much better low-frequency performance than randomized-scrambling encoders.
The general idea is to use the analog sources equally often, even when evaluated over short time periods. Story proposed that the analog sources be considered mapped onto an oriented circle and used sequentially (like the digits on a conventional clock), whereby the difference between the number of times that each analog source has been used will always be zero or one. This concept, which is called the element-rotation scheme (ERS), is illustrated in FIG. 5 for a sequence of 10 samples. It can be observed that the selection of which unit elements to use is uniquely defined by
1. the orientation of the rotation (which is always the same),
2. the first element to use for the D/A conversion of the present sample (the so-called rotation pointer, which in FIG. 5 is shown with a shade), and
3. the number of elements to use (i.e., the value of d(k)).
FIG. 7 shows a simple state machine implementing an ERS digital encoder [40] for use in a 8-unit-element ERS D/A converter. It is based on the observation that the rotation pointer can be calculated as the integral (summation) of the digital input signal d(k) modulo the number of unit elements, which in this case is 8. It is assumed that the digital input signal d(k) is binary encoded and restricted to attain only integer values in the range from 0 through 8, including both the values 0 and 8. A 3-bit adder [42] and a delay element [44] implement the operation of a delaying integrator for which the output, i.e., the rotation pointer c(k)=c1(k)+c2(k)+c3(k), is calculated modulo 8. The modulo-8 operation is obtained by discarding any overflow information, which usually is represented by the adder""s [42] xe2x80x9ccarry-out bitxe2x80x9d (not shown). A binary-to-thermometer (B2T) encoder [46] produces 8 intermediate signals, b1(k), b2(k), . . . , b8(k), each having either the value 0 or 1, according to the truth table shown in FIG. 6. The sum of the bi(k) signals equals d(k), and the highest index of the nonzero bi(k) signals equals d(k). The rotation pointer c(k) represents how much the thermometer code generated by the B2T encoder [46] is to be rotated. The rotation operation is implemented in 3 steps using 3 demultiplexers [48],[50], and [52]. The rotation pointer""s most significant bit, c3(k), will attain only the values 0 and 4. It controls the rotate-by-0/4 demultiplexer [48] which generates 8 signals mi(k) as a rotated (by 0 or 4 tabs) permutation of the bi(k) signals. The rotate-by-0/4 demultiplexer""s [48] operation is described by the truth table shown in FIG. 8. The rotation pointer""s two less significant bits, c2(k) and c1(k), will attain values 0/2 and 0/1 respectively. They are used to control the demultiplexers [50] and [52] which generate the digital subsignals di(k) as rotated perturbations of the signals mi(k) provided by the rotate-by-0/4 demultiplexer [48]. The truth tables for these demultiplexers [50] and [52] are shown in FIGS. 9 and 10.
3.4 Idle Tones in Mismatch-Shaping Unit-Element D/A Converters
It can be shown that the error signal e(k)=a(k)xe2x88x92{circumflex over (K)}d(k) from an ERS mismatch-shaping D/A converter is the first-order difference of a signal s(k), i.e., e(k)=s(k)xe2x88x92s(kxe2x88x921). The signal s(k) is a deterministic, memoryless, time-invariant, and nonlinear function of the rotation pointer c(k). More precisely, the value of s(k) depends only on the instant value of c(k). The static, but generally unknown, relationship between s(k) and c(k) reflects the mismatch of the analog sources in a specific implementation (two implementations will generally not be characterized by the same relationship, as they represent two outcomes of a stochastic process).
Many derivations used to analyze ERS D/A converters are based on the assumption that s(k) has uniform spectral power density, which is desirable. This assumption may be justifiable if the rotation pointer c(k) is a broadband signal that does not include any tones. However, due to the very simple relationship between the input signal d(k) and the rotation pointer c(k), periodicity/tonality of d(k) unfortunately, but usually, implies that c(k) will have a nonuniform autocorrelation function, i.e., the assumption is not justified. Considering that d(k) is the signal to be D/A converted, which for a wide range of applications will be periodic or at least pseudo-periodic (i.e., include short-term patterns), it should be understood that the above assumption is likely to lead to misleading predictions of the D/A converter""s performance.
FIGS. 11, 12, and 13 shows the simulated spectral composition of a 16-unit-element ERS D/A converter""s error signal e(k), when it is applied different types of input signals d(k). FIG. 11 shows the performance for a periodic input signal. In this example, d(k) was a sinusoid signal which was truncated to 4-bit resolution by simply neglecting the least significant bits (LSBs). Clearly, the error signal e(k) is composed of only discrete tones, which is highly undesirable. The D/A converter""s 4-bit resolution is too coarse for most practical applications, and hence d(k) will generally be the output from a multibit delta-sigma (xcex94xcexa3) modulator. The xcex94xcexa3 modulator is used to interpolate a high-resolution oversampled signal into a lower-resolution representation d(k). Even for periodic input signals, the xcex94xcexa3 modulator will generate an aperiodic output signal d(k). This property reflects that the xcex94xcexa3 modulator""s input and output signals are equivalent in the signalband only. In other words, the xcex94xcexa3 modulator""s input signal is truncated to a lower resolution output signal d(k) by adding an aperiodic noise-like signal component, which has negligible power in the signal band. The inclusion of an aperiodic signal component tends to spectrally spread the rotation pointer""s energy, but as shown in FIG. 12, the ERS D/A converter""s error signal can be tonal even when it is driven by a xcex94xcexa3 modulator.
Such tones are called idle tones. Idle tones are indeed a problem to be concerned about because they may significantly deteriorate the SNR performance. The significance of the SNR degradation is exemplified by FIG. 4 in a paper by Fujimori [xe2x80x9cA 1.5 V 4.1 mW Dual Channel Audio Delta-Sigma D/A Converterxe2x80x9d, Ichiro Fujimori and Tetsuro Sugimoto, IEEE Journal of Solid-State Circuits, Vol. 33, No. 12, December 1998]. Clearly, the signals produced by xcex94xcexa3 modulators may not be sufficiently aperiodic to avoid the deleterious effects from idle tones.
FIG. 13 shows the error signal""s spectral composition when the input signal d(k) is a white-noise random signal. The error signal""s e(k) spectral power density is approximately proportional to the frequency, which is the desired performance. Unfortunately, only few applications require D/A conversion of random signals, and hence ERS D/A converters will generally suffer from idle-tone problems.
3.4.1 Dithered Mismatch-Shaping Unit-Element D/A Converters
U.S. Pat. No. 5,404,142 to Bob Adams describes an alternative mismatch-shaping encoder (called a mismatch-shaping butterfly scrambler) which tends to produce less idle tones than ERS encoders. Similarly, U.S. Pat. No. 5,684,482 to Ian Galton describes a tree-structured digital encoder which also tends to produce less idle tones than ERS encoders. Both Adams and Galton describe so-called dithering techniques, which can make their respective encoders virtually idle-tone-free. These dithering techniques are efficient, but they can be used only with the respective encoders, which are significantly more complex to implement than, for example, ERS encoders.
Louis A. Williams described [An Audio DAC with 90 dB Linearity using MOS to Metal-Metal Charge Transfer, Louis A. Williams III, Digest of Technical Papers for the IEEE 1998 International Solid-State Circuits Conference, Vol. 41, San Francisco, Feb. 5,6, and 7, 1998] a mismatch-shaping encoder, which he called a grouped-level-averaging (GLA) encoder, that consists of three ERS encoders multiplexed as a function of the input signal. GLA encoders are fairly simple to implement, and they tend to produce less idle tones than ERS encoders. GLA encoders, however, are not entirely idle-tone-free, and an efficient dithering technique has not been suggested.
In accordance with the present invention, idle tones in mismatch-shaping encoders can be suppressed by randomly permuting the digital subsignals whenever the encoder encounters a state for which the accumulated error is zero.
4.1 Objects and Advantages
Accordingly, several objects and advantages of the present invention are
to provide a low-complexity mismatch-shaping encoder for use with unit-element D/A converters;
to provide a mismatch-shaping encoder which, when used to drive a unit-element D/A converter, does not produce deleterious idle tones;
to provide a mismatch-shaping encoder which is more efficient than GLA encoders in the sense that the error signal comprises relatively less power in the signal band;
to provide a dithering technique which can be used to suppress idle tones in any type of mismatch-shaping encoder;
to provide a dithering technique which can be used for mismatch-shaping encoders that minimize the error signal in any predefined frequency range.
Further objects and advantages will become apparent from a consideration of the ensuing description and drawings.